1. Field of the Invention
The present invention relates to a polysilicon thin film transistor (herein after referred to as a TFT) and a method for manufacturing the same, and, more particularly, to a method for manufacturing a polysilicon TFT of which reduces the electric field near the drain junction is reduced by varying the thickness of a gate insulating layer through a post oxidation process.
2. Description of the Related Art
TFTs are mainly used as switching elements of pixels in a liquid crystal display (herein after referred to as an LCD) and are classified into two types based on the material used as an active layer of the TFT. One type used amorphous silicon as the active layer of the TFT. One type uses amorphous silicon as the active layer, while the other type uses polysilicon. Since LCDs with the amorphous silicon TFTs are light and thin, and have low power consumption and good image quality as well, they are used in various portable electronic devices such as the notebook computers. Since the amorphous silicon TFT can be fabricated at a temperature below 600.degree. C. which is the strain point of glass, it is possible to use glass as a substrate of an LCD panel. And since price of the glass is lower than that of the quartz, both of which are used as substrates of LCDs, the cost can, therefore, be lower. However, since the device characteristics of an amorphous silicon TFT is inferior to that of a polysilicon TFT, an amorphous TFT cannot be applied to circuits requiring high operation speed.
Since the polysilicon TFT has a carrier mobility higher than that of the amorphous silicon TFT, polysilicon TFT driving circuits can be integrated on the LCD panel. Further, the polysilicon TFT LCD does not require optical shielding, which is inevitable in the amorphous silicon TFT LCD due to the photo leakage current of the amorphous silicon. Also, the polysilicon TFT is suitable for the LCDs with large size and high density, particularly, since it is possible to form the driving circuits on the panel, the size of polysilicon TFT LCD can be miniaturized.
Polysilicon has small single-crystalline regions called grains. The silicon atoms in the interior of the grain are arranged periodically, as in a single crystalline silicon, but the atoms around the boundaries of the grains are arranged in a non-periodic fashion, resulting in incomplete bondings and thus many defects. Since the interior of the grain has a perfect crystalline structure, the polysilicon has mobility superior to the amorphous silicon, which has no crystalline structure. However, the polysilicon has narrow energy gaps, and a lot of dangling bonds exist in the grain boundaries. These defects, located in the center of the energy band gap, contribute to the creations of the carriers and serve as the center of the recombinations of the carriers. Consequently, there is a problem that leakage currents are produced, particularly near the drain junction which is under a high electric field.
A conventional polysilicon TFT will now be described in detail with reference to FIG. 1, which shows a cross sectional view of a top gate type conventional polysilicon TFT in which a gate electrode lies on over an insulator that is on an active layer.
An active layer 12 made of polysilicon is formed on a transparent glass substrate 11, and a gate insulating layer 13 made of silicon oxide is formed thereon. A gate electrode 14 is formed on the gate insulating layer 13 and is covered with an insulating film 15. Both the gate insulating layer 13 and the insulating film 15 have two contact holes through which a source and a drain electrodes 16 and 17, respectively, are contacted with the active layer 12.
The polysilicon TFT of this structure has a disadvantage in that leakage currents are larger than those of the amorphous silicon TFT. The leakage currents are generated by the tunneling of the carriers under the strong electric field around the junction of a drain region and a channel region (hereinafter referred to as a drain junction) in the active layer. The on-current probability of tunneling is determined by the density of the traps in the polysilicon. Since the polysilicon has lots of traps, the leakage currents are large. In order to reduce these leakage currents, methods for lowering the electric fields near the drain junction are generally used. One of the latter methods is to adopt a lightly-doped drain (hereinafter referred to as an LDD) structure.
An LDD structure is formed by using sidewalls or a photoresist layer as masks for implanting LDD ions. For the sake of reducing the leakage currents effectively, the length of the LDD region would ideally be about 1-2 .mu.m, but it is very difficult to make the LDD with such a small length when using sidewalls as a mask. It is also difficult to obtain a reproducible LDD structure when using a photoresist since the self-alignment is not possible in the photolithography. Moreover, there is a problem in the LDD structure that on-current is reduced suddenly.